SETS Recruitment 2019 – Research Associate and Junior Research Fellow Posts

Details regarding the posts, vacancies, educational qualification, salary, age limit and selection process are given below in a brief manner, kindly go through it carefully.

Candidates are requested to produce all original certificates (UG / PG degrees, age proof, experience certificate, publications and any other testimonials that certify their competency to work in the project) and apply Online (by mail).

Society for Electronic Transactions and Security Placement Details

Vacancies : 

• Society for Electronic Transactions and Security requires following posts to fill their vacancies.

1. Research Associate – 01.
2. Junior Research Fellow – 02.

Placement : 

• Chennai (Tamilnadu).

Society for Electronic Transactions and Security Job Eligibility Details : 

Educational Qualification : 

1. Research Associate –

• PhD in Engineering/Science in the relevant area of the project or
• M.E/M.Tech in Microelectronics and Photonics/Laser and Electro Optics/Electronics and Communication Engineering/VLSI Design/Digital Electronics/Embedded Systems/ or equivalent from a recognized university with First Class or equivalent with at least 3 years of relevant experience.
• Desirable Skills/ Knowledge :
  a) Knowledge of Quantum Communication and Information.
  b) Hands-on experience in optical communication interfaces.
  c) Knowledge of Xilinx FPGA implementation flow and tools.
  d) Knowledge of FPGA realization and control softwares.

    2. Junior Research Fellow –

• M.E/M.Tech in Electronics and Communication Engineering/Digital Electronics/Embedded Systems/VLSI Design/Microelectronics and Photonics/Laser and Electro Optics/ or equivalent from a recognized university with First Class or equivalent.
• Areas of Skill sets/ Knowledge required :
  a) Knowledge of Xilinx FPGA implementation flow and tools.
  b) Hands-on experience in simulation using MATLAB/ModelSim and FPGA realization using VHDL/Verilog programming.
  c) Knowledge of clock, memory, DCM, and I/O management and implementation on
  FPGAs (desirable).
  d) Experience in design integration, FPGA I/O communications and testing (desirable).

Age Limit : 

• Not Mentioned. 

Salary Details : 

1. Research Associate – Rs 47000 p.m. plus 24% HRA.
2. Junior Research Fellow – Rs 31000 p.m. plus 24% HRA.
3. Upon satisfactory performance, RA will be paid Rs 49000 p.m. plus 24% HRA for the 2 nd year and Rs 54000 p.m. plus 24% HRA for the 3rd year. The JRF will become SRF after two years and will be paid Rs 35000 p.m. plus 24% HRA for the 3rd year. Other rules apply as per prevailing DST norms.

Mode of Applying : 

• Online.

Duration of Project :

• 3 years.

Selection Process : 

1. Written Test.
2. Personal Interview.
3. Document Verification.

Important Dates : 

• Last date for submission of online application : 15.06.2019.
• Email : [email protected]
• Candidate should write “Application for the post of __________ for QKD Project of DST” in the subject line of his/her E-mail.

How to apply for SETS Recruitment 2019 –  Research Associate and Junior Research Fellow Posts

• Check and verify your eligibility to SETS  Recruitment 2019.
• Submit all the details required by Society for Electronic Transactions and Security.
• Go through the Official Notification carefully.
• Visit SETS official website https://setsindia.in
• The candidate is required to send the filled-in Personal Particulars Form (Available in the website) by email to [email protected]
• Candidate should write “Application for the post of __________ for QKD Project of DST” in the subject line of his/her E-mail.

Download SETS Recruitment 2019 Official Notification and Apply Online

SETS Official Notification : Click Here

SETS Application Form : Click Here